The present invention relates to the field of use of high speed computer networking. More particularly, the present invention relates to methods and apparatus for allowing flexibility of network data source and destination as well as alleviation of memory bus traffic through the support of one or more system bus target devices, where each device can have different bus characteristics.
2. Description of Related Art
Presently, a computer system connects to and communicates with other computer systems in a computer network through the use of network adapters. A network adapter typically has two connections, one to the computer network and another to the input/output (I/O) bus of the computer system. Through the use of the I/O bus, the network adapter communicates with the host processor of the computer system which in turn is connected to a host memory through the use of a memory bus. The network adapter also communicates with other components of the computer system using the I/O bus, which include such devices as storage device interfaces, frame buffers, coprocessors, Erasable Programmable Read Only Memories (EPROM""s) and network physical layer devices.
One function of the network adapter is to transfer data between the host memory and the network. The data contained in the host memory which is to be transferred is packetized. Each packet is composed of a header section and a data section. When the host processor needs to transfer data from the host memory out onto the network, the network adapter is responsible for reading the portion of the host memory that contains the packets, performing any necessary processing of the packets into a suitable form for transfer and sending the data out onto the network.
Storage of the outgoing data in host memory before it is transferred to the network adapter effectively doubles the number of transfers that is accomplished over the memory bus. In addition to increasing the demand on the processing resources of the host processor, the multiplicity of transfers is also inefficient use of both the bandwidths of the host memory and the I/O bus. These problems are exacerbated in situations where the computer system needs to provide a constant stream of data from the host memory to the network adapter.
Alternatively, instead of being contained in the host memory, the packets to be transferred can be completely contained in a second device on the I/O bus. However, this approach also has associated problems. For example, the header portions of a packet is processed by the host processor of the computer system. If the data to be transferred is completely contained in the memory of the second I/O device, then either the network adapter or the second I/O device has to incorporate processing circuitry to process the header or other special control portions of the packets to be transferred.
Examples of the problems associated with current approaches to dealing with the storage and transferring of network data can be seen where the I/O bus of the computer system is a bus conforming to the Institute of Electronics and Electrical Engineers (IEEE) 1496-1993 SBus specification and the network conforms to an asynchronous transfer mode (ATM) network. ATM is a high-speed, connection-oriented switching and multiplexing technology that uses cells to transmit different types of data traffic simultaneously. These different types of traffic may include voice and video data in addition to traditional computer data. For example, in a video conference session using computer systems that contain audio and video digitizing capability, the host computer can transfer voice and video along with other data over the ATM network. ATM is asynchronous in that information streams can be sent independently without a common clock.
In multimedia applications where the computer system is acting as a multifunctional resource controller such as an audio/video server, image storage and data routing, the data stream composing the audio and video requested by a client computer system usually constitute a large amount of data. As it would be uneconomical to build computer systems with host memory large enough to store the amount of data required, this multimedia data is contained one or more SBus storage devices and must be loaded into the host memory in portions small enough to fit in the host memory. Each portion of multimedia data is then transferred over the SBus, by the host computer, to the network adapter to be segmented and packaged into cells to be delivered over the ATM network before the next portion is loaded into host memory. As the amount of the multimedia data requested becomes larger, the host processor has to devote more and more of its processing resources to satisfy the request. Also, if the data to be loaded into the host memory is distributed over more than one storage device, the host processor must spend time loading the data from different sources.
Moreover, in the multimedia application, the majority of the memory bus bandwidth and resources will be monopolized by the intensive network data transfer requirements and cannot be used for other processing needs. This is because of the large amount of network data contained in host memory which has to be transferred to the network adapter. Conversely, if the memory bus is being used to service other memory requests, and thus is unavailable for transferring network data, it will be difficult to maintain a constant transfer of the data that is contained inside the host memory to the network adapter.
In cases where the data is split over several SBus storage devices, each portion can be directly transferred from the SBus storage device to the network adapter. However, as mentioned before, extra cost will be incurred in providing the extra processing circuitry in either the SBus storage devices or the network adapter needed to process the header and other special control portions of the packet. Moreover, the network adapter has to devote a portion of its resources to process the control portions of the packet, which results in a loss of performance.
In solving the inefficiency and loss of system performance caused by storing all the network data in either the host memory or a second bus target device, the present invention provides a method and apparatus for allowing data which comprise a packet to be spread over numerous storage devices, including the host memory. The present invention can (1) acquire and assemble the data comprising the header and data portions of the packets to be transferred over a computer network from several sources; and (2) distribute and divide the data received from the computer network over several local bus devices, including the host memory. The present invention is able to achieve the above capabilities with no wasted bus cycles even when the devices over which the data is distributed have different bus characteristics.
By allowing packet data to be spread over both host memory and one or more separate bus target devices, the present invention reduces the load on the system memory bus and allows more efficient use of memory bus bandwidth. For example, if the amount of network data that has to be transferred from the host memory is reduced, thus releasing the memory bus for other processing needs. Also, it will be easier to provide a constant stream of data to the computer network as a majority of the resources of the memory bus does not have to be dedicated for transferring network data.
The present invention achieves the above functions by using a network adapter which contains an I/O bus interface, a burst dispatcher, a synchronization and buffering logic, and a network media interface. The I/O bus interface is responsible for sending and receiving data to and from the I/O bus and can also initiate bus transactions. The burst dispatcher generates a control word for each bus cycle that controls bus characteristics of the next bus transaction that is performed by the I/O bus interface. This control word is based on the characteristics of the device with which the data is to be exchanged. The network media interface prepares the data for transmission over the network media. The synchronization and buffering logic acts as a buffer to store (1) the data received from the I/O bus interface before it is transmitted to the network media interface, and (2) the data received from the network media interface before it is transmitted to the I/O bus interface. The synchronization and buffering logic buffers the data until-the cycle during which each respective interface is ready to receive the data.
In operation, the host processor initializes a set of I/O configuration registers inside the network adapter at system initialization to contain the I/O transfer characteristics of each device connected to an I/O bus. During normal transmit operations where the data is being sent to the computer network, host processor would create one descriptor entry for each portion of each packet to be transmitted from the computer. The host processor would then pass the descriptor entries to the network adapter and the network adapter would be responsible for reading the data from the bus target device described by the descriptor entry using the I/O bus interface and burst dispatcher. The data that is read by the I/O bus interface is then passed to the synchronization and buffering logic, which sends the data to the network media interface.
Other objects, features and advantages of the present invention will be apparent from the accompanying drawings, and from the detailed description that follows below.